The present invention relates to an output driver for use in a semiconductor device, and more particularly, to an output driver effectively performing an impedance matching operation.
An output driver is a circuit for driving an output pad to which a predetermined load is connected in order to output a data from a semiconductor device. Generally, a push-pull type driver is widely used as the output driver. The push-pull type driver has a form of a CMOS inverter constituted with a pull-up PMOS transistor and a pull-down NMOS transistor serially connected each other between a power supply voltage VDD terminal and a ground voltage VSS terminal.
FIG. 1 is a detailed circuit diagram illustrating a conventional output driver.
Referring FIG. 1, the conventional output driver includes a pre-drive unit 100 and a main drive unit 120. The pre-drive unit 100 generates drive control signals PU_DRV_CTRL and PD_DRV_CTRL based on a data signal DATA. The main drive unit 120 drives an output terminal DQ in response to the control signals PU_DRV_CTRL and PD_DRV_CTRL.
The pre-drive unit 100 includes a pull-up pre-drive unit 102 and a pull-down pre-drive unit 104. The pull-up pre-drive unit 102 generates the pull-up drive control signal PU_DRV_CTRL; and the pull-down pre-drive unit 104 generates the pull-down drive control signal PD_DRV_CTRL. The pull-up pre-drive unit 102 includes a pull-up inverter PU_INV for inverting the data signal DATA by using a power supply voltage VDD and a ground voltage VSS and outputting the pull-up drive control signal PU_DRV_CTRL. The pull-down pre-drive unit 104 includes a pull-down inverter PD_INV for inverting the data signal DATA by using the power supply voltage VDD and the ground voltage VSS and outputting the pull-down drive control signal PD_DRV_CTRL.
The main drive unit 120 includes a pull-up main drive unit 122 and a pull-down main drive unit 124. The pull-up main drive unit 122 performs a pull-up drive operation to the output terminal DQ in response to the pull-up drive control signal PU_DRV_CTRL outputted from the pull-up pre-drive unit 102. The pull-down main drive unit 124 performs a pull-down drive operation to the output terminal DQ in response to the pull-down drive control signal PD_DRV_CTRL outputted from the pull-down pre-drive unit 104. The pull-up main drive unit 122 includes a pull-up PMOS transistor PU_PMOS and a pull-up resistor PU_R. The pull-up PMOS transistor PU_PMOS, connected between a power supply voltage VDD terminal and the pull-up resistor PU_R, receives the pull-up drive control signal PU_DRV_CTRL through its gate. The pull-up PMOS transistor PU_PMOS is connected to the output terminal DQ through the pull-up resistor PU_R. The pull-down main drive unit 124 includes a pull-down NMOS transistor PD_NMOS and a pull-down resistor PD_R.
The pull-down NMOS transistor PD_NMOS, connected between a ground voltage VSS terminal and the pull-down resistor PD_R, receives the pull-down drive control signal PD_DRV_CTRL through its gate. The pull-down NMOS transistor PD_NMOS is connected to the output terminal DQ through the pull-down resistor PD_R.
Hereinafter, an operation of the output driver with abovementioned structure will be described.
Firstly, in case that the data signal DATA has a logic high level of a power supply voltage VDD level, the pull-up pre-drive unit 102 inverts the data signal DATA and outputs the pull-up drive control signal PU_DRV_CTRL of a logic low level corresponding to a ground voltage VSS level. The pull-down pre-drive unit 104, also, inverts the data signal DATA and outputs the pull-down drive control signal PD_DRV_CTRL of the logic low level corresponding to the ground voltage VSS level. The pull-up PMOS transistor PU_PMOS in the pull-up main drive unit 122 is turned on in response to the pull-up drive control signal PU_DRV_CTRL of the logic low level and provides the output terminal DQ with the power supply voltage VDD. However, the pull-down NMOS transistor PD_NMOS receiving the pull-down drive control signal PD_DRV_CTRL of the logic low level is turned off and cannot provide the output terminal DQ with the ground voltage VSS. Therefore, the output terminal DQ has the logic high level of the power supply voltage VDD level when the data signal DATA is the logic high level.
Next, in case that the data signal DATA has a logic low level of the ground voltage VSS level, the pull-up pre-drive unit 102 inverts the data signal DATA and outputs the pull-up drive control signal PU_DRV_CTRL of the logic high level corresponding to the power supply voltage VDD level. The pull-down pre-drive unit 104, also, inverts the data signal DATA and outputs the pull-down drive control signal PD_DRV_CTRL of the logic high level corresponding to the power supply voltage VDD level. The pull-up PMOS transistor PU_PMOS receiving the pull-up drive control signal PU_DRV_CTRL of the logic high level is turned off. The pull-down NMOS transistor PD_NMOS is turned on in response to the pull-down drive control signal PD_DRV_CTRL of the logic high level and provides the output terminal DQ with the ground voltage VSS. Therefore, the output terminal DQ has the logic low level of the ground voltage VSS level when the data signal DATA is the logic low level.
Meanwhile, the pull-up resistor PU_R and the pull-down resistor PD_R are passive elements and their resistances are fixed without concerning the state of the control signals. However, by being connected between the pull-up PMOS transistor PU_PMOS and the output terminal DQ and between the pull-down NMOS transistor PD_NMOS and the output terminal DQ, respectively, the pull-up resistor PU_R and the pull-down resistor PD_R make an output signal, outputted through the output terminal DQ, linearly changed. That is, the pull-up resistor PU_R and the pull-down resistor PD_R are used for impedance matching with an output terminal to which the output signal is transmitted. For example, the resistance of the output terminal DQ of the DDR3 SDRAM is defined as “34Ω±10%” in the Specification for the reliable data transmission. In other words, if the resistance of the output terminal DQ of the DDR3 SDRAM is out of the range of “34Ω±10%”, the reliable data transmission cannot be ensured.
The resistance of the output terminal DQ is determined not only by the pull-up resistor PU_R and the pull-down resistor PD_R but also by the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS. When the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS are turned on, the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS affects to the resistance of the output terminal. Therefore, the total resistance of the output terminal DQ is determined by adding the resistance of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS, which are turned on, to the resistance of the pull-up resistor PU_R and the pull-down resistor PD_R.
FIG. 2A is a waveform diagram illustrating the current amount flowing through the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS according to the power supply voltage VDD level.
Referring to FIG. 2A, when the power supply voltage VDD level decreases from about 1.7V to about 1.0V, the absolute value of the current amount IDD flowing through the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS decreases from about 2.5 mA to 1.0 mA. The decrease of the current amount IDD means that the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS increase as the power supply voltage VDD level decreases.
FIG. 2B is a waveform diagram illustrating the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS according to the power supply voltage VDD level.
Referring to FIG. 2B, when the power supply voltage VDD level decreases from about 1.7V to about 1.0V, the absolute value of the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS dramatically increase from about 33Ω to about 50Ω.
The data shown in FIGS. 2A and 2B are the result when the output driver shown in FIG. 1 is applied to the DDR3 SDRAM.
As a result, the current amount IDD flowing through the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS decrease and the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS increases as the power supply voltage VDD level decreases. That is, the distribution of the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS are out of the range of “34Ω±10%”, and, therefore, the conventional output driver shown in FIG. 1 is hardly possible to match the impedance between the output terminal and the input terminal to which the output signal is transmitted. For example, although the resistance of the output terminal DQ is adjusted to about 35Ω based on the power supply voltage VDD level of about 1.5V, the resistance of the output terminal DQ easily changes to about 60Ω when the power supply voltage VDD level decreases to about 1.0V. Therefore, it is meaningless to adjust the resistances of the pull-up resistor PU_R and the pull-down resistor PD_R for the impedance matching operation based on the power supply voltage VDD level of 1.5V. As mentioned above, the conventional output driver cannot ensure a reliable data transmission because of the radical change of the resistances of the pull-up PMOS transistor PU_PMOS and the pull-down NMOS transistor PD_NMOS in the main drive unit 120.